Supported RISC-V ISA Extensions
The following RISC-V ISA extensions are supported. The *_ENABLE column names the synthesis-time parameter that removes a mechanism from the design entirely (both simulation and real synthesis) where one exists – every such combination is verified end-to-end by verif/enable_matrix.
| Extension | Description | *_ENABLE |
|---|---|---|
I |
Base RV64I integer ISA (all 64-bit ops incl. *W 32-bit forms) | – |
M |
Multiply/divide (RV64M): combinational multiply, multi-cycle restoring divide | – |
A |
Atomics (RV64A): AMO* + LR/SC | – |
F |
Single-precision floating point (RV64F) | – |
D |
Double-precision floating point (RV64D), incl. multi-cycle FDIV/FSQRT | – |
Zfa |
Additional FP ops: FLI.S/FLI.D, FMINM/FMAXM, FROUND/FROUNDNX, FCVTMOD.W.D, FLEQ/FLTQ | – |
C |
Compressed (RVC): 16-bit instructions expanded to RV64 in fetch | – |
V |
Vector with VLEN=512: integer/FP arithmetic, reductions, mask/permutation ops | – |
H |
Hypervisor: nested virtualization, VS-level state, G-stage second-stage translation | – |
Zicsr |
CSR access instructions; baseline for all CSR interfaces (incl. the entropy-source CSRs) | – |
Zifencei |
Instruction-fetch fence (FENCE.I) for I-cache coherence |
– |
Zba |
Bitmanip: address-calculation instructions (implemented in the ALU) | – |
Zbb |
Bitmanip: basic bit-manipulation instructions (implemented in the ALU) | – |
Zbs |
Bitmanip: single-bit instructions (implemented in the ALU) | – |
Zicond |
Branchless conditional zeroing (CZERO.EQZ/CZERO.NEZ, implemented in the ALU) |
– |
Zicbom |
Cache-block management: CBO.INVAL/CLEAN/FLUSH (architectural no-ops – no cache exists) |
– |
Zicboz |
CBO.ZERO: real multi-cycle 64-byte block write |
– |
Zihintpause |
PAUSE hint (decodes as a NOP on this in-order core) |
– |
Zicbop |
PREFETCH.R/W/I hints (decode as NOPs – no cache exists) |
– |
Zawrs |
Wait-for-reservation-set WRS.* (decode as immediate-return NOPs) |
– |
Zkt |
Data-independent execution timing for integer ops (holds by construction) | – |
Sstc |
Supervisor-mode Timer Compare extension | – |
Smaia |
Machine-mode AIA CSRs for the advanced interrupt architecture (APLIC/IMSIC) | – |
Ssaia |
Supervisor-mode AIA CSRs | – |
Sv39 |
39-bit virtual memory (3-level page tables) | – |
Sv48 |
48-bit virtual memory (4-level page tables) | – |
Sv57 |
57-bit virtual memory (5-level page tables) | – |
Svade |
A/D bits set by software: with ADUE=0, a leaf PTE that would otherwise succeed but has A=0 (or D=0 on write/AMO) raises a genuine page fault for the OS to fix up |
– |
Svadu |
A/D bits set by hardware: with ADUE=1 (the reset default), the walker atomically updates a leaf PTE’s A/D bits in place – both extensions coexist, selected at runtime per translation stage |
– |
Svinval |
SINVAL.VMA selective invalidation with SFENCE.VMA’s exact selectivity |
– |
Svpbmt |
Page-based memory types via the PTE PBMT field (folded into the walker’s fault path) |
– |
Svnapot |
Ratified 64 KiB NAPOT page-table encoding (folded into the walker) | – |
Zicfilp |
Forward-edge CFI: LPAD landing pads; a non-exempt JALR arms an expected-landing-pad state enforced on the next fetch (software-check exception, mcause=18) |
– |
Zicfiss |
Backward-edge CFI: dedicated shadow stack (ssp, SSPUSH/SSPOPCHK) with its own PTE encoding; a mismatched pop raises the software-check exception |
– |
Ssdbltrp/Smdbltrp |
Double-trap detection: per-privilege sticky trap-in-flight bits redirect an unexpected trap one level up (mcause=16, suppressed cause in mtval2); M-level halts the hart in a permanent critical-error state |
– |
Zvkb |
Vector crypto bit-manipulation: VANDN/VROL/VROR/VBREV8/VREV8/VWSLL | – |
Zvkt |
Data-independent vector execution latency (holds by construction on the serial engine) | – |
Zvkned |
Vector AES-256 block cipher | ZVKNED_ENABLE |
Zvkg |
Vector AES-256-GCM/GMAC authenticated encryption | ZVKG_ENABLE |
Zvknhb |
Vector SHA2-256/384/512 hash | ZVKNHB_ENABLE |
Zvknhk |
Vector SHA3/Keccak (draft proposal, not yet ratified) | ZVKNHK_ENABLE |
PMP |
Physical Memory Protection mechanism | PMP_ENABLE |
Smepmp |
M-mode PMP enhancement: mseccfg RLB/MML/MMWP lock and write-restriction rules |
PMP_ENABLE |
IOPMP |
I/O Physical Memory Protection for DMA devices | IOPMP_ENABLE |
Zkr |
The scalar entropy-source seed CSR (0x015, wipe-on-read, OPST status bits) on top of the hardware entropy source; access gated by mseccfg.sseed/.useed |
– |