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    <title>i-RISCV SBI Firmware</title>
    <link>https://i-riscv.org/sbi/index.html</link>
    <description>The i-RISCV SoC provides two M-mode boot-firmware paths that reach the exact same kernel image from the same device tree. The default path uses upstream OpenSBI, genuinely unmodified; the alternate path is this project’s own standalone SBI implementation. Which firmware runs is selected purely by the linux_boot Makefile target: check/image (and their 72 variants) use OpenSBI, check-sbi/image-sbi (and their 72 variants) the standalone SBI.&#xA;OpenSBI (default) A pinned, unmodified upstream OpenSBI release built with PLATFORM=generic – recognized purely through OpenSBI’s own FDT drivers matching the SoC’s device tree nodes (serial@10000000, clint@2000000, plic0), with zero source customization A tiny SoC-specific M-mode prestage programs the entropy-source FUSE bank and jumps directly into OpenSBI’s fw_jump entry point – still in M-mode, no mret All standard boot setup (medeleg/mideleg, menvcfg, mcounteren, PMP) is performed by OpenSBI itself, computed from the hart’s detected extensions – including trap-safe PMP probing on builds where PMP is disabled Standalone SBI (alternate) A from-scratch M-mode firmware implementing the modern SBI v2.0 extension set:</description>
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