https://i-riscv.org/io/index.html The i-RISCV SoC provides the following input/output mechanisms. IOMMU The SoC implements the RISC-V IOMMU (v1.0) for DMA-capable devices. Supported mechanisms: Device Directory Table (DDT) walk in Off, Bare, 1LVL, 2LVL, and 3LVL modes Second-stage-only DMA address translation (Sv39x4/Sv48x4/Sv57x4) with hardware A/D update on page-table entries MSI address translation, redirecting a device’s writes to a guest’s virtual IMSIC interrupt file onto the real physical guest file (AIA/IMSIC tie-in) IOATC: a device-context cache and an I/O TLB, invalidated via IODIR.INVAL_DDT and IOTINVAL.VMA/.GVMA commands Command queue (IOTINVAL, IOFENCE.C, IODIR) and fault queue for translation errors WSI (wire-signal) interrupt delivery to the PLIC/APLIC on faults or fence completion IOPMP enforcement of the final physical address after every successful translation AIA and IMSIC The core implements the RISC-V Advanced Interrupt Architecture (AIA, v1.0). Supported mechanisms: Hugo en-us