https://i-riscv.org/cpu_internals/index.html The i-RISCV core is a single-issue, in-order processor. The following mechanisms are supported. Pipeline A six-stage pipeline (IF1/IF2/ID/EX/MEM/WB) with synchronous instruction and data memory access. flowchart LR IF1["IF1<br/>PC gen"] --> IF2["IF2<br/>imem data phase"] IF2 --> ID["ID<br/>decode + reg read"] ID --> EX["EX<br/>ALU / branch resolve"] EX --> MEM["MEM<br/>dmem addr phase,<br/>CSR r/w, traps"] MEM --> WB["WB<br/>dmem data phase,<br/>regfile commit"] Supported mechanisms: Hugo en-us