i-RISCV - The inferred RISC-V SoC

A production-ready RVA23U64 RISC-V SoC. Every mechanism is real, verified hardware: it boots an unmodified Linux kernel out of simulation, and its cryptographic implementations pass NIST ACVP validation.

i-RISCV provides a CPU implementing the RISC-V instruction set architecture (ISA) along with a large set of RISC-V extensions.

Why i-RISCV

• Full RVA23U64 profile. RV64IMAFDCV with hypervisor (H), vector crypto (Zvk*), AIA interrupts, and IOMMU – every mechanism is real hardware verified end to end, not a teaching core.
• Configurable at synthesis time. Every optional mechanism – the four Zvk* crypto units, the entropy source, the branch predictor, PMP, IOPMP, the FUSE controller, and the UART – is gated by its own build-time *_ENABLE parameter: set it to 0 and the hardware is removed from the design entirely, not merely tied off. Single-core or multi-core (NUM_HARTS) is likewise a synthesis-time choice.
• Boots real Linux. Unmodified upstream OpenSBI plus stock, unmodified Linux v6.6 and v7.2: full extension detection, Sstc timer from S-mode, real UART console, KVM initialization.
• Fully tested, fully documented. Unit tests, directed assembly tests through the real pipeline, a build-permutation matrix, RISCOF conformance, differential fuzzing harness, NIST ACVP crypto validation – with complete design documentation for every mechanism.

Author

Stephan Mueller smueller@chronox.de